EDA电子设计自动化实验（软实验）——实验4 有限状态机设计

实验内容

1. 设计一个交通红绿灯控制器模块，实现主干道和支路之间红绿黄灯的信号转换。
2. 设计一个10层楼的电梯控制器模块，要求：(1) 时间先后优先级；(2)位置先后优先级。
3. 设计一个10位计算器(+,-,*,/)，要有BCD码转换，共阴极LED笔画显示部分实现。

1. 设计一个交通红绿灯控制器模块，实现主干道和支路之间红绿黄灯的信号转换

状态机结构框图：

实验模块代码：

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY TRAFFIC IS
    PORT(CLK,RST:IN STD_LOGIC;
        MLIGHTS,CLIGHTS:OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END TRAFFIC;
ARCHITECTURE BEHAV OF TRAFFIC IS
TYPE STATES IS (S0,S1,S2,S3);

    SIGNAL C_ST,N_ST:STATES:=S0;
    SIGNAL TIME0:STD_LOGIC_VECTOR(6 DOWNTO 0);
    BEGIN
    COUNT:PROCESS(CLK,RST)
    VARIABLE T:STD_LOGIC_VECTOR(6 DOWNTO 0);        --加法计数器模块
        BEGIN
        IF RST='1' THEN T:=(OTHERS=>'0');
        ELSIF CLK'EVENT AND CLK='1' THEN 
            IF(T<68) THEN T:=T+1;
            ELSE T:=(OTHERS=>'0');
            END IF;
        END IF;
        TIME0<=T;
    END PROCESS COUNT;
    
    REG:PROCESS(CLK,RST)
        BEGIN
        IF RST='1' THEN C_ST<=S0;
        ELSIF CLK'EVENT AND CLK='1' THEN C_ST<=N_ST;
        END IF;
    END PROCESS REG;    
    
    COM:PROCESS(C_ST,TIME0)
        BEGIN
        CASE C_ST IS
        WHEN S0 => MLIGHTS<="100";CLIGHTS<="001";
            IF TIME0=39 THEN N_ST<=S1;
            ELSE N_ST<=S0;
            END IF;
        WHEN S1 => MLIGHTS<="010";CLIGHTS<="010";
            IF TIME0=43 THEN N_ST<=S2;
            ELSE N_ST<=S1;
            END IF;
        WHEN S2 => MLIGHTS<="001";CLIGHTS<="100";
            IF TIME0=63 THEN N_ST<=S3;
            ELSE N_ST<=S2;
            END IF;
        WHEN S3 => MLIGHTS<="010";CLIGHTS<="010";
            IF TIME0=67 THEN N_ST<=S0;
            ELSE N_ST<=S3;
            END IF;
        END CASE;
    END PROCESS COM;
END BEHAV;

TestBench：

LIBRARY ieee;                                               
USE ieee.std_logic_1164.all;                                
ENTITY TRAFFIC_vhd_tst IS
END TRAFFIC_vhd_tst;
ARCHITECTURE TRAFFIC_arch OF TRAFFIC_vhd_tst IS
                                              
SIGNAL CLK : STD_LOGIC;
SIGNAL MLIGHTS : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL RST : STD_LOGIC;
SIGNAL CLIGHTS : STD_LOGIC_VECTOR(2 DOWNTO 0);
CONSTANT CLK_P:TIME:= 100 NS;
COMPONENT TRAFFIC
    PORT (
    CLK : IN STD_LOGIC;
    MLIGHTS : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
    RST : IN STD_LOGIC;
    CLIGHTS : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
    );
END COMPONENT;
BEGIN
    i1 : TRAFFIC
    PORT MAP (
    CLK => CLK,
    MLIGHTS => MLIGHTS,
    RST => RST,
    CLIGHTS => CLIGHTS
    );
init : PROCESS  
BEGIN
        CLK<='0' ;WAIT FOR CLK_P;
        CLK<='1' ;WAIT FOR CLK_P;
END PROCESS init;              
RST<='1','0' AFTER 2 US;                                                    
END TRAFFIC_arch;

占用资源（Cyclone IV GX EP4CGX15BF14C6 ）：

当交通灯信号分别用以下数据表示时占用器件资源如下：

二进制：

独热码：

格雷码：

仿真波形（信号灯用独热码形式）：

状态图：

实验结果及分析：

实验采用one-hot编码方式作为信号灯的编码，其中“100”表示绿灯，“010”表示黄灯，“001”表示红灯。MLIGHTS表示主干道交通灯信号，CLIGHTS表示支路交通灯信号（题目假设只有一条主干道和一条支路）。理想情况下，主干道每次通行时间为40s，支路每次通行时间20s，黄灯每次等待4s，即68s为一个周期。

根据仿真波形结果可知设计程序正确。

2. 设计一个10层楼的电梯控制器模块

状态机结构框图：

实验模块代码：

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ELEVATOR IS
    PORT(CLK,RST:IN STD_LOGIC;
        FLOOR:IN STD_LOGIC_VECTOR(10 DOWNTO 1);
        POSITION:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); 
END ELEVATOR;
ARCHITECTURE BEHAV OF ELEVATOR IS
TYPE STATES IS (S0,S1,S2,S3,S4,S5,S6,S7,S8);

    SIGNAL C_ST,N_ST:STATES:=S0;
    SIGNAL UP_DOWN,UD:STD_LOGIC:='0'; --0上升，1下降
    BEGIN
    COM:PROCESS(C_ST,FlOOR,UP_DOWN,RST)
    VARIABLE P:STD_LOGIC_VECTOR(3 DOWNTO 0);
        BEGIN
        IF RST='1' THEN P:="0001";
        END IF;
        CASE C_ST IS
        WHEN S0 => 
            IF FLOOR="0000000000" THEN N_ST<=S0;            --楼层用一位热码编码方式
            ELSIF UP_DOWN='0' THEN
                IF P="0001" THEN 
                    IF (FLOOR(2) OR FLOOR(3) OR FLOOR(4) OR FLOOR(5) OR FLOOR(6) 
                        OR FLOOR(7) OR FLOOR(8) OR FLOOR(9) OR FLOOR(10))='0' THEN UD<='1';
                    END IF;
                ELSIF P="0010" THEN 
                    IF (FLOOR(3) OR FLOOR(4) OR FLOOR(5) OR FLOOR(6) 
                        OR FLOOR(7) OR FLOOR(8) OR FLOOR(9) OR FLOOR(10))='0' THEN UD<='1';
                    END IF;
                ELSIF P="0011" THEN 
                    IF (FLOOR(4) OR FLOOR(5) OR FLOOR(6) 
                        OR FLOOR(7) OR FLOOR(8) OR FLOOR(9) OR FLOOR(10))='0' THEN UD<='1';
                    END IF;
                ELSIF P="0100" THEN 
                    IF (FLOOR(5) OR FLOOR(6) 
                        OR FLOOR(7) OR FLOOR(8) OR FLOOR(9) OR FLOOR(10))='0' THEN UD<='1';
                    END IF;
                ELSIF P="0101" THEN 
                    IF (FLOOR(6) OR FLOOR(7) OR FLOOR(8) OR FLOOR(9) OR FLOOR(10))='0' THEN UD<='1';
                    END IF;
                ELSIF P="0110" THEN 
                    IF (FLOOR(7) OR FLOOR(8) OR FLOOR(9) OR FLOOR(10))='0' THEN UD<='1';
                    END IF;
                ELSIF P="0111" THEN 
                    IF (FLOOR(8) OR FLOOR(9) OR FLOOR(10))='0' THEN UD<='1';
                    END IF;
                ELSIF P="1000" THEN 
                    IF (FLOOR(9) OR FLOOR(10))='0' THEN UD<='1';
                    END IF;
                ELSIF P="1001" THEN 
                    IF FLOOR(10)='0' THEN UD<='1';
                    END IF;
                ELSIF P="1010" THEN UD<='1';
                END IF;
                N_ST<=S3;
            ELSIF UP_DOWN='1' THEN
                IF P="1010" THEN 
                    IF (FLOOR(9) OR FLOOR(8) OR FLOOR(7) OR FLOOR(6) OR FLOOR(5) 
                        OR FLOOR(4) OR FLOOR(3) OR FLOOR(2) OR FLOOR(1))='0' THEN UD<='0';
                    END IF;
                ELSIF P="1001" THEN 
                    IF (FLOOR(8) OR FLOOR(7) OR FLOOR(6) OR FLOOR(5) 
                        OR FLOOR(4) OR FLOOR(3) OR FLOOR(2) OR FLOOR(1))='0' THEN UD<='0';
                    END IF;
                ELSIF P="1000" THEN 
                    IF (FLOOR(7) OR FLOOR(6) OR FLOOR(5) 
                        OR FLOOR(4) OR FLOOR(3) OR FLOOR(2) OR FLOOR(1))='0' THEN UD<='0';
                    END IF;
                ELSIF P="0111" THEN 
                    IF (FLOOR(6) OR FLOOR(5) 
                        OR FLOOR(4) OR FLOOR(3) OR FLOOR(2) OR FLOOR(1))='0' THEN UD<='0';
                    END IF;
                ELSIF P="0110" THEN 
                    IF (FLOOR(5) OR FLOOR(4) OR FLOOR(3) OR FLOOR(2) OR FLOOR(1))='0' THEN UD<='0';
                    END IF;
                ELSIF P="0101" THEN 
                    IF (FLOOR(4) OR FLOOR(3) OR FLOOR(2) OR FLOOR(1))='0' THEN UD<='0';
                    END IF;
                ELSIF P="0100" THEN 
                    IF (FLOOR(3) OR FLOOR(2) OR FLOOR(1))='0' THEN UD<='0';
                    END IF;
                ELSIF P="0011" THEN 
                    IF (FLOOR(2) OR FLOOR(1))='0' THEN UD<='0';
                    END IF;
                ELSIF P="0010" THEN 
                    IF FLOOR(1)='0' THEN UD<='0';
                    END IF;
                ELSIF P="0001" THEN UD<='0';
                END IF;
                N_ST<=S3;
            END IF;
            POSITION<=P;
        WHEN S1 => 
            IF FLOOR="0000000000" THEN N_ST<=S0;
            ELSE

                    P:=P+1;
                    IF FLOOR(CONV_INTEGER(P))='1' THEN N_ST<=S0;
                    ELSE N_ST<=S7;
                    END IF;
            END IF;
        WHEN S2 => 
            IF FLOOR="0000000000" THEN N_ST<=S0;
            ELSE
                    P:=P-1;
                    IF FLOOR(CONV_INTEGER(P))='1' THEN N_ST<=S0;
                    ELSE N_ST<=S8;
                    END IF;
            END IF;
        WHEN S3 => N_ST<=S4;
        WHEN S4 => N_ST<=S5;
        WHEN S5 => N_ST<=S6;
        WHEN S6 =>
            IF UP_DOWN='0' THEN N_ST<=S1;
            ELSIF UP_DOWN='1' THEN N_ST<=S2;
            END IF;
        WHEN S7 => N_ST<=S1;
        WHEN S8 => N_ST<=S2;
        END CASE;
    END PROCESS COM;
    
    REG:PROCESS(CLK,UD,RST)
        BEGIN
        IF RST='1' THEN C_ST<=S0;
        ELSIF CLK'EVENT AND CLK='1' THEN UP_DOWN<=UD;C_ST<=N_ST;
        END IF;
    END PROCESS REG;
END BEHAV;

TestBench：

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY ELEVATOR_vhd_tst IS
END ELEVATOR_vhd_tst;
ARCHITECTURE ELEVATOR_arch OF ELEVATOR_vhd_tst IS                                                  
SIGNAL CLK,RST : STD_LOGIC;
SIGNAL FLOOR : STD_LOGIC_VECTOR(10 DOWNTO 1);
SIGNAL POSITION : STD_LOGIC_VECTOR(3 DOWNTO 0);
CONSTANT CLK_P:TIME:=1 us;

COMPONENT ELEVATOR
    PORT(CLK,RST:IN STD_LOGIC;
        FLOOR:IN STD_LOGIC_VECTOR(10 DOWNTO 1);
        POSITION:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;

BEGIN
    i1 : ELEVATOR PORT MAP(CLK => CLK, RST => RST, FLOOR => FLOOR, POSITION => POSITION);
    PROCESS
        BEGIN
        CLK<='0'; WAIT FOR CLK_P;
        CLK<='1'; WAIT FOR CLK_P;
    END PROCESS;
    
    RST<='1','0' AFTER 2 us;
    FLOOR<="1010000110","0000000000" AFTER 72 us,"0010000011" AFTER 90 us,"0000000000" AFTER 152 us;
END ELEVATOR_arch;

占用资源（Cyclone IV GX EP4CGX15BF14C6 ）：

用二进制数表示当前所处楼层，用one-hot码表示选择的前往楼层。

仿真波形：

实验结果及分析：

用二进制数表示当前所处楼层，用one-hot码表示选择的前往楼层。

FLOOR为输入，输入为要前往的各楼层数，可以选择多层。

POSITION为当前所处的楼层数。

根据仿真波形可得，设计程序正确。

3、设计一个10位计算器(+,-,*,/)，要有BCD码转换，共阴极LED笔画显示部分实现

状态机结构框图：

实验模块代码：

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY CALCULATOR IS
    PORT(AIN,BIN:IN STD_LOGIC_VECTOR(9 DOWNTO 0);
        CLK:IN STD_LOGIC;
        CH:IN STD_LOGIC_VECTOR(1 DOWNTO 0);
        A,B,C,D,E,F,G:OUT STD_LOGIC_VECTOR(0 TO 6));
END ENTITY;
ARCHITECTURE BEHAV OF CALCULATOR IS
TYPE STATES IS (JIA,JIAN,CHENG,CHU);

    SIGNAL C_ST,N_ST:STATES:=JIA;
    SIGNAL RESULT:STD_LOGIC_VECTOR(19 DOWNTO 0);
    SIGNAL BCD:STD_LOGIC_VECTOR(27 DOWNTO 0);
    BEGIN
    COM:PROCESS(AIN,BIN,CH,C_ST)
    VARIABLE DATA:STD_LOGIC_VECTOR(19 DOWNTO 0);
        BEGIN
        DATA:="00000000000000000000";
        CASE C_ST IS
        WHEN JIA => DATA(10 DOWNTO 0):=('0'&AIN)+('0'&BIN);RESULT<=DATA;
            IF CH="00" THEN N_ST<=JIA;
            ELSIF CH="01" THEN N_ST<=JIAN;
            ELSIF CH="10" THEN N_ST<=CHENG;
            ELSIF CH="11" THEN N_ST<=CHU;
            END IF;
        WHEN JIAN => DATA(9 DOWNTO 0):=AIN-BIN;RESULT<=DATA;
            IF CH="00" THEN N_ST<=JIA;
            ELSIF CH="01" THEN N_ST<=JIAN;
            ELSIF CH="10" THEN N_ST<=CHENG;
            ELSIF CH="11" THEN N_ST<=CHU;
            END IF;
        WHEN CHENG => DATA:=AIN*BIN;RESULT<=DATA;
            IF CH="00" THEN N_ST<=JIA;
            ELSIF CH="01" THEN N_ST<=JIAN;
            ELSIF CH="10" THEN N_ST<=CHENG;
            ELSIF CH="11" THEN N_ST<=CHU;
            END IF;
        WHEN CHU => DATA(4 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(CONV_INTEGER(AIN)/CONV_INTEGER(BIN),5);RESULT<=DATA;
            IF CH="00" THEN N_ST<=JIA;
            ELSIF CH="01" THEN N_ST<=JIAN;
            ELSIF CH="10" THEN N_ST<=CHENG;
            ELSIF CH="11" THEN N_ST<=CHU;
            END IF;
        END CASE;       
    END PROCESS COM;
    REG:PROCESS(CLK)
        BEGIN
        IF CLK'EVENT AND CLK='1' THEN C_ST<=N_ST;
        END IF;
    END PROCESS REG;
    BCDT:PROCESS(RESULT)
    VARIABLE TEMP:INTEGER;
    VARIABLE DATA_TEMP:INTEGER;
    VARIABLE BCD_TEMP:STD_LOGIC_VECTOR(27 DOWNTO 0);
        BEGIN
        BCD_TEMP:=(OTHERS=>'0');
        DATA_TEMP:=CONV_INTEGER(RESULT);
        FOR K IN 0 TO 6 LOOP
            TEMP:=DATA_TEMP REM 10;
            BCD_TEMP(3+4*K DOWNTO 4*K):=CONV_STD_LOGIC_VECTOR(TEMP,4);
            DATA_TEMP:=(DATA_TEMP-TEMP)/10;
            IF DATA_TEMP=0 THEN EXIT;
            END IF;
        END LOOP;
        BCD<=BCD_TEMP;
    END PROCESS BCDT;
    WITH BCD(3 DOWNTO 0) SELECT
        A<="1111110" WHEN "0000","0110000" WHEN "0001",
                "1101101" WHEN "0010","1111001" WHEN "0011",
                "0110011" WHEN "0100","1011011" WHEN "0101",
                "1011111" WHEN "0110","1110000" WHEN "0111",
                "1111111" WHEN "1000","1111011" WHEN "1001",
                "0000000" WHEN OTHERS;
        WITH BCD(7 DOWNTO 4) SELECT
        B<="1111110" WHEN "0000","0110000" WHEN "0001",
                "1101101" WHEN "0010","1111001" WHEN "0011",
                "0110011" WHEN "0100","1011011" WHEN "0101",
                "1011111" WHEN "0110","1110000" WHEN "0111",
                "1111111" WHEN "1000","1111011" WHEN "1001",
                "0000000" WHEN OTHERS;
        WITH BCD(11 DOWNTO 8) SELECT
        C<="1111110" WHEN "0000","0110000" WHEN "0001",
                "1101101" WHEN "0010","1111001" WHEN "0011",
                "0110011" WHEN "0100","1011011" WHEN "0101",
                "1011111" WHEN "0110","1110000" WHEN "0111",
                "1111111" WHEN "1000","1111011" WHEN "1001",
                "0000000" WHEN OTHERS;
        WITH BCD(15 DOWNTO 12) SELECT
        D<="1111110" WHEN "0000","0110000" WHEN "0001",
                "1101101" WHEN "0010","1111001" WHEN "0011",
                "0110011" WHEN "0100","1011011" WHEN "0101",
                "1011111" WHEN "0110","1110000" WHEN "0111",
                "1111111" WHEN "1000","1111011" WHEN "1001",
                "0000000" WHEN OTHERS;
        WITH BCD(19 DOWNTO 16) SELECT
        E<="1111110" WHEN "0000","0110000" WHEN "0001",
                "1101101" WHEN "0010","1111001" WHEN "0011",
                "0110011" WHEN "0100","1011011" WHEN "0101",
                "1011111" WHEN "0110","1110000" WHEN "0111",
                "1111111" WHEN "1000","1111011" WHEN "1001",
                "0000000" WHEN OTHERS;
        WITH BCD(23 DOWNTO 20) SELECT
        F<="1111110" WHEN "0000","0110000" WHEN "0001",
                "1101101" WHEN "0010","1111001" WHEN "0011",
                "0110011" WHEN "0100","1011011" WHEN "0101",
                "1011111" WHEN "0110","1110000" WHEN "0111",
                "1111111" WHEN "1000","1111011" WHEN "1001",
                "0000000" WHEN OTHERS;
        WITH BCD(27 DOWNTO 24) SELECT
        G<="1111110" WHEN "0000","0110000" WHEN "0001",
                "1101101" WHEN "0010","1111001" WHEN "0011",
                "0110011" WHEN "0100","1011011" WHEN "0101",
                "1011111" WHEN "0110","1110000" WHEN "0111",
                "1111111" WHEN "1000","1111011" WHEN "1001",
                "0000000" WHEN OTHERS;
END BEHAV;

TestBench：

LIBRARY ieee;                                               
USE ieee.std_logic_1164.all;                                
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY CALCULATOR_vhd_tst IS
END CALCULATOR_vhd_tst;
ARCHITECTURE CALCULATOR_arch OF CALCULATOR_vhd_tst IS
-- constants                                                 
-- signals                                                   
SIGNAL A : STD_LOGIC_VECTOR(0 TO 6);
SIGNAL AIN : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL B : STD_LOGIC_VECTOR(0 TO 6);
SIGNAL BIN : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL C : STD_LOGIC_VECTOR(0 TO 6);
SIGNAL CH : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL CLK : STD_LOGIC;
SIGNAL D : STD_LOGIC_VECTOR(0 TO 6);
SIGNAL E : STD_LOGIC_VECTOR(0 TO 6);
SIGNAL F : STD_LOGIC_VECTOR(0 TO 6);
SIGNAL G : STD_LOGIC_VECTOR(0 TO 6);
CONSTANT CLK_P:TIME:= 100 us;
COMPONENT CALCULATOR
    PORT (
    A : OUT STD_LOGIC_VECTOR(0 TO 6);
    AIN : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
    B : OUT STD_LOGIC_VECTOR(0 TO 6);
    BIN : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
    C : OUT STD_LOGIC_VECTOR(0 TO 6);
    CH : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
    CLK : IN STD_LOGIC;
    D : OUT STD_LOGIC_VECTOR(0 TO 6);
    E : OUT STD_LOGIC_VECTOR(0 TO 6);
    F : OUT STD_LOGIC_VECTOR(0 TO 6);
    G : OUT STD_LOGIC_VECTOR(0 TO 6)
    );
END COMPONENT;
BEGIN
    i1 : CALCULATOR
    PORT MAP (
-- list connections between master ports and signals
    A => A,
    AIN => AIN,
    B => B,
    BIN => BIN,
    C => C,
    CH => CH,
    CLK => CLK,
    D => D,
    E => E,
    F => F,
    G => G
    );
init : PROCESS                                                                                   
BEGIN                                                        
    CLK<= '0'; WAIT FOR CLK_P;
    CLK<= '1'; WAIT FOR CLK_P;                                                  
END PROCESS init;                                           
    AIN<=CONV_STD_LOGIC_VECTOR(12,10), CONV_STD_LOGIC_VECTOR(25,10) AFTER 20 ms;
    BIN<=CONV_STD_LOGIC_VECTOR(2,10), CONV_STD_LOGIC_VECTOR(5,10) AFTER 20 ms;
    CH<= "00","01" AFTER 10 ms, "10" AFTER 20 ms,"11" AFTER 30 ms;
END CALCULATOR_arch;

占用资源（Cyclone IV GX EP4CGX22CF19C6 ）：

仿真波形图：

实验结果及分析：

AIN、BIN、CH为输入。

其中CH为要进行的运算方法：

当CH输入“00”时，进行加法运算，输出结果等于AIN+BIN；

当CH输入“01”时，进行减法运算，输出结果等于AIN-BIN；

当CH输入“10”时，进行乘法运算，输出结果等于AIN*BIN；

当CH输入“11”时，进行除法运算，输出结果等于AIN/BIN（若理论结果不为整数，则应向下取整）。

最后输出A、B、C、D、E、F、G七组7位标准逻辑矢量，作为显示结果的7个七段数码管的输入。

根据仿真波形可知，设计程序正确。