EDA电子设计自动化实验（软实验）——实验1 加法器设计

实验内容

设计一个16位二进制全加器模块。
用层次化设计方法，设计一个16位二进制全加器模块。
设计一个16位二进制超前进位全加器模块。
设计一个16-bit 8421-BCD码全加器模块。

1. 设计一个16位二进制全加器模块

实验原理：使用并位符“&”使输入成为17位标准逻辑矢量，用于方便得到进位输出，即输入相加得到的结果的最高位即为进位输出，低16位即为相加结果。

实验模块代码：

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY ADD16B IS
    PORT (AIN,BIN : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
            CIN : IN STD_LOGIC ;
            COUT : OUT STD_LOGIC;
            SUM : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
    );
END ENTITY ADD16B;

ARCHITECTURE ADD OF ADD16B IS 
SIGNAL DATA : STD_LOGIC_VECTOR (16 DOWNTO 0 );
    BEGIN 
            DATA <= ('0'& AIN) + ('0' & BIN) + (CONV_STD_LOGIC_VECTOR(0,16) & CIN);
            COUT <= DATA(16);
            SUM <= DATA(15 DOWNTO 0);
END ARCHITECTURE ADD;

TestBench：

LIBRARY ieee;                                               
USE ieee.std_logic_1164.all;                                
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY ADD16B_vhd_tst IS
END ADD16B_vhd_tst;
ARCHITECTURE ADD16B_arch OF ADD16B_vhd_tst IS
-- constants                                                 
-- signals                                                   
SIGNAL AIN : STD_LOGIC_VECTOR(15 DOWNTO 0) :=CONV_STD_LOGIC_VECTOR(12,16);
SIGNAL BIN : STD_LOGIC_VECTOR(15 DOWNTO 0) :=CONV_STD_LOGIC_VECTOR(1,16);
SIGNAL CIN : STD_LOGIC :='0';
SIGNAL COUT : STD_LOGIC ;
SIGNAL SUM : STD_LOGIC_VECTOR(15 DOWNTO 0);
COMPONENT ADD16B
    PORT (
    AIN : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ;
    BIN : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ;
    CIN : IN STD_LOGIC;
    COUT : BUFFER STD_LOGIC;
    SUM : BUFFER STD_LOGIC_VECTOR(15 DOWNTO 0) 
    );
END COMPONENT;
BEGIN

    AIN <= CONV_STD_LOGIC_VECTOR(12,16),    CONV_STD_LOGIC_VECTOR(13,16) AFTER 100 NS, CONV_STD_LOGIC_VECTOR(51000,16) AFTER 200 NS;
    BIN <= CONV_STD_LOGIC_VECTOR(1,16),     CONV_STD_LOGIC_VECTOR(30,16) AFTER 150 NS, CONV_STD_LOGIC_VECTOR(20000,16)  AFTER 200 NS;
    CIN <='0', '1' AFTER 150 NS, '0' AFTER 300 NS;
    
    U1 : ADD16B
    PORT MAP (
    AIN => AIN,
    BIN => BIN,
    CIN => CIN,
    COUT => COUT,
    SUM => SUM
    );
                                                                                     
END ADD16B_arch;

仿真波形如下：

结果：输出结果正常，进位正常。

2. 用层次化设计方法，设计一个16位二进制全加器模块

实验原理：通过元件例化语句实现多层调用，可以将小位数的加法器连接成大位数的加法器。

四位加法器模块：

ADD4.vhd

LIBRARY IEEE;
use ieee.std_logic_1164.all;

entity add4 is
port(a,b:in std_logic_vector(3 downto 0);
        ci:in std_logic;
        s:out std_logic_vector(3 downto 0);
        co:out std_logic);
end entity;
        architecture add_4 of add4 is
        SIGNAL c0,c1,c2:std_logic;
        begin   
            s(0) <= a (0) xor b(0) xor ci;
            c0<= (a(0) and b(0)) or (a(0) and ci) or (b(0) and ci);
            
            s(1) <= a (1) xor b(1) xor c0;
            c1<= (a(1) and b(1)) or (a(1) and c0) or (b(1) and c0);
            
            s(2) <= a (2) xor b(2) xor c1;
            c2<= (a(2) and b(2)) or (a(2) and c1) or (b(2) and c1);
            
            s(3) <= a (3) xor b(3) xor c2;
            co<= (a(3) and b(3)) or (a(3) and c2) or (b(3) and c2);
        end architecture add_4;

八位加法器模块（例化两个4位加法器）：

ADD8.vhd

LIBRARY IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity add8 is
port(a8,b8:in std_logic_vector(7 downto 0);
        ci8:in std_logic;
        s8:out std_logic_vector(7 downto 0);
        co8:out std_logic);
end entity;
        architecture add_8 of add8 is
        component add4 is
        port(a,b:in std_logic_vector(3 downto 0);
        ci:in std_logic;
        s:out std_logic_vector(3 downto 0);
        co:out std_logic);
        end component;
        
        
        signal c:std_logic;
    begin

        add8_1: add4
        port map(a=>a8(3 downto 0),b=>b8(3 downto 0),s=>s8(3 downto 0),ci=>ci8,co=>c);
        
        add8_2:add4
        port map(a=>a8(7 downto 4),b=>b8(7 downto 4),s=>s8(7 downto 4),ci=>c,co=>co8);

        end architecture add_8;

十六位加法器模块（例化两个8位加法器）:

ADD16B_CM.vhd

LIBRARY IEEE;
use ieee.std_logic_1164.all;

entity ADD16B_CM is
    PORT (AIN,BIN : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
    CIN : IN STD_LOGIC ;
    COUT : OUT STD_LOGIC;
    SUM : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END ADD16B_CM;
ARCHITECTURE BEHAV OF ADD16B_CM IS 
COMPONENT add8
port(a8,b8:in std_logic_vector(7 downto 0);
ci8:in std_logic;
s8:out std_logic_vector(7 downto 0);
co8:out std_logic);
END COMPONENT;

SIGNAL DATA : STD_LOGIC_VECTOR(16 DOWNTO 0);
SIGNAL C : STD_LOGIC;
BEGIN 
add16_1: add8
port map(a8=>AIN(7 DOWNTO 0),b8=>BIN(7 downto 0),s8=>SUM(7 downto 0),ci8=>CIN,co8=>C);
add16_2:add8
port map(a8=>AIN(15 downto 8),b8=>BIN(15 downto 8),s8=>SUM(15 downto 8),ci8=>C,co8=>COUT);

end BEHAV;

TestBench：

LIBRARY ieee;                                               
USE ieee.std_logic_1164.all;       
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY ADD16B_CMtb_vhd_tst IS
END ADD16B_CMtb_vhd_tst;
ARCHITECTURE ADD16B_CM_arch OF ADD16B_CMtb_vhd_tst IS
                                               
SIGNAL AIN : STD_LOGIC_VECTOR(15 DOWNTO 0) :=CONV_STD_LOGIC_VECTOR(0,16);
SIGNAL BIN : STD_LOGIC_VECTOR(15 DOWNTO 0) :=CONV_STD_LOGIC_VECTOR(0,16);
SIGNAL CIN : STD_LOGIC :='0';
SIGNAL COUT : STD_LOGIC;
SIGNAL SUM : STD_LOGIC_VECTOR(15 DOWNTO 0);
COMPONENT ADD16B_CM
    PORT (
    AIN : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
    BIN : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
    CIN : IN STD_LOGIC;
    COUT : OUT STD_LOGIC;
    SUM : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
    );
END COMPONENT;
BEGIN
    U1 : ADD16B_CM
    PORT MAP (

    AIN => AIN,
    BIN => BIN,
    CIN => CIN,
    COUT => COUT,
    SUM => SUM
    );

    AIN <= CONV_STD_LOGIC_VECTOR(12,16),    CONV_STD_LOGIC_VECTOR(13,16) AFTER 100 NS, CONV_STD_LOGIC_VECTOR(50000,16) AFTER 200 NS;
    BIN <= CONV_STD_LOGIC_VECTOR(1,16),     CONV_STD_LOGIC_VECTOR(30,16) AFTER 150 NS, CONV_STD_LOGIC_VECTOR(20000,16)  AFTER 200 NS;
    CIN <='0', '1' AFTER 150 NS, '0' AFTER 300 NS;
    
                                      
END ADD16B_CM_arch;

仿真波形：

结果：输出结果正常，进位正常。